HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 308

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 8 Interrupt Controller (INTC)
Table 8.2
Note:
As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit
groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)
are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F means priority level 15 (the highest level).
Page 248 of 1414
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
* Reserved. Always read as 0. The write value should always be 0. The SSL and SDHI-
related bits are effective only for the models that include them. Reserved bits apply if
they are not included.
Interrupt Sources and IPRA to IPRJ
Bits 15 to 12
TMU0
WDT
IRQ3
Reserved*
DMAC (1)
ADC
SCIF0
PINTA
SIOF0
Reserved*
Bits 11 to 8
TMU1
REF
IRQ2
TMU (TMU_SUNI) IRQ5
Reserved*
DMAC (2)
SCIF1
PINTB
SIOF1
USBH
SIM
Bits 7 to 4
TMU2
IRQ1
LCDC
USBF
Reserved*
TPU
MMC
SDHI
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Bits 3 to 0
RTC
Reserved*
IRQ0
IRQ4
SSL
CMT
Reserved*
I
PCC
AFEIF
2
C
Sep 21, 2010

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