HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 248

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Memory Management Unit (MMU)
• Software (TLB Miss Handler) Operations
4.5.2
A TLB protection violation exception results when the virtual address and the address array of the
selected TLB entry are compared and a valid entry is found to match, but the type of access is not
permitted by the access rights specified in the PR field. TLB protection violation exception
processing includes both hardware and software operations.
• Hardware Operations
Page 188 of 1414
The software searches the page tables in external memory and allocates the required page table
entry. Upon retrieving the required page table entry, software must execute the following
operations:
A. Write the value of the physical page number (PPN) field and the protection key (PR), page
B. If using software for way selection for entry replacement, write the desired value to the RC
C. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
D. Issue the return from exception handler (RTE) instruction to terminate the handler routine
In a TLB protection violation exception, this hardware executes a set of prescribed operations,
as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the
D. The PC value indicating the address of the instruction in which the exception occurred is
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that generated the exception is set in the RC field in MMUCR.
size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table
entry recorded in the address translation table in the external memory into the PTEL
register.
field in MMUCR.
and return to the instruction stream. Issue the RTE instruction after issuing two instructions
from the LDTLB instruction.
EXPEVT register.
written into SPC (if the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written into SPC).
TLB Protection Violation Exception
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010