ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 317
ATMEGA128-16AU
Manufacturer Part Number
ATMEGA128-16AU
Description
IC AVR MCU 128K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA128-16AU.pdf
(26 pages)
2.ATMEGA128-16AU.pdf
(385 pages)
3.ATMEGA128-16AU.pdf
(389 pages)
Specifications of ATMEGA128-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128-16AU
Manufacturer:
MITSUBISHI
Quantity:
104
Company:
Part Number:
ATMEGA128-16AU
Manufacturer:
ATMEL
Quantity:
3 340
Part Number:
ATMEGA128-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Virtual Flash Page Read
Register
Programming Algorithm
2467M–AVR–11/04
Figure 150. Virtual Flash Page Load Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the
number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the
data are automatically transferred from the Flash data page byte by byte. The first eight
cycles are used to transfer the first byte to the internal Shift Register, and the bits that
are shifted out during these 8 cycles should be ignored. Following this initialization, data
are shifted out starting with the LSB of the first instruction in the page and ending with
the MSB of the last instruction in the page. This provides an efficient way to read one full
Flash page to verify programming.
Figure 151. Virtual Flash Page Read Register
All references below of type “1a”, “1b”, and so on, refer to Table 130.
TDO
TDO
TDI
TDI
D
D
A
T
A
A
T
A
machine
machine
State
State
STROBES
STROBES
ADDRESS
ADDRESS
EEPROM
EEPROM
Lock Bits
Lock Bits
Fuses
Fuses
Flash
Flash
ATmega128
317
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