ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 131

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Timer/Counter
Register Description
Timer/Counter1 Control
Register A – TCCR1A
Timer/Counter3 Control
Register A – TCCR3A
2467M–AVR–11/04
•
•
•
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA,
OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are writ-
ten to one, the OCnA output overrides the normal port functionality of the I/O pin it is
connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of
the COMnC1:0 bits are written to one, the OCnC output overrides the normal port func-
tionality of the I/O pin it is connected to. However, note that the Data Direction Register
(DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to
enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0
bits is dependent of the WGMn3:0 bits setting. Table 58 shows the COMnx1:0 bit func-
tionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Table 58. Compare Output Mode, non-PWM
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
COMnA1/COMnB1/
COMnC1
0
0
1
1
COM1A1
COM3A1
R/W
R/W
7
0
7
0
COM3A0
COM1A0
R/W
R/W
6
0
6
0
COMnA0/COMnB0/
COM3B1
COM1B1
COMnC0
R/W
R/W
5
0
5
0
0
1
0
1
COM3B0
COM1B0
R/W
R/W
4
0
4
0
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on compare
match.
Clear OCnA/OCnB/OCnC on compare
match (set output to low level).
Set OCnA/OCnB/OCnC on compare match
(set output to high level).
COM1C1
COM3C1
R/W
R/W
3
0
3
0
COM1C0
COM3C0
R/W
R/W
2
0
2
0
WGM11
WGM31
ATmega128
R/W
R/W
1
0
1
0
WGM10
WGM30
R/W
R/W
0
0
0
0
TCCR1A
TCCR3A
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