ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 226

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multi-master Systems
and Arbitration
226
ATmega128
If multiple masters are connected to the same bus, transmissions may be initiated simul-
taneously by one or more of them. The TWI standard ensures that such situations are
handled in such a way that one of the masters will be allowed to proceed with the trans-
fer, and that no data will be lost in the process. An example of an arbitration situation is
depicted below, where two masters are trying to transmit data to a slave receiver.
Figure 105. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
•
•
•
This is summarized in Figure 106. Possible status values are given in circles.
SDA
SCL
Two or more masters are performing identical communication with the same slave.
In this case, neither the slave nor any of the masters will know about the bus
contention.
Two or more masters are accessing the same slave with different data or direction
bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data
bits. The masters trying to output a one on SDA while another master outputs a zero
will lose the arbitration. Losing masters will switch to not addressed slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
Two or more masters are accessing different slaves. In this case, arbitration will
occur in the SLA bits. Masters trying to output a one on SDA while another master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
slave mode to check if they are being addressed by the winning master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
TRANSMITTER
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
Device 3
RECEIVER
SLAVE
........
Device n
V
CC
R1
2467M–AVR–11/04
R2