ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 304

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Serial Programming
Algorithm
304
ATmega128
Figure 144. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
When writing serial data to the ATmega128, data is clocked on the rising edge of SCK.
When reading data from the ATmega128, data is clocked on the falling edge of SCK.
See Figure 145 for timing details.
To program and verify the ATmega128 in the SPI Serial Programming mode, the follow-
ing sequence is recommended (See four byte instruction formats in Table 145):
1. Power-up sequence:
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-
Apply power between V
some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
As an alternative to using the RESET signal, PEN can be held low during Power-
on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on
Reset is important. If the programmer cannot guarantee that SCK is held low
during power-up, the PEN method cannot be used. The device must be powered
down in order to commence normal operation when using this method.
gramming Enable serial instruction to pin MOSI.
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock
2. V
source to the XTAL1 pin.
CC
- 0.3V < AVCC < V
PDO
SCK
PDI
CC
ck
ck
and GND while RESET and SCK are set to “0”. In
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
PE0
PE1
PB1
XTAL1
RESET
GND
+ 0.3V, however, AVCC should always be within 2.7 - 5.5V.
(1)
AVCC
VCC
+2.7 - 5.5V
+2.7 - 5.5V
(2)
ck
ck
≥ 12 MHz
≥ 12 MHz
2467M–AVR–11/04