ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 17

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRAM Data Memory
2467M–AVR–11/04
The ATmega128 supports two different configurations for the SRAM data memory as
listed in Table 1.
Table 1. Memory Configurations
Figure 9 shows how the ATmega128 SRAM Memory is organized.
The ATmega128 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the
ATmega128 is in the ATmega103 compatibility mode.
In normal mode, the first 4352 Data Memory locations address both the Register file, the
I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, then 160 loca-
tions of Extended I/O memory, and the next 4096 locations address the internal data
SRAM.
In ATmega103 compatibility mode, the first 4096 Data Memory locations address both
the Register file, the I/O Memory and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, and the next
4000 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega128. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. The Register file, I/O, Extended I/O
and Internal SRAM occupies the lowest 4352 bytes in normal mode, and the lowest
4096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so when
using 64KB (65536 bytes) of External Memory, 61184 Bytes of External Memory are
available in normal mode, and 61440 Bytes in ATmega103 compatibility mode. See
“External Memory Interface” on page 24 for details on how to take advantage of the
external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
two-byte program counter is pushed and popped, and external memory access does not
take advantage of the internal pipe-line memory access. When external SRAM interface
is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruc-
tion set manual for one, two, and three wait-states.
Configuration
Normal mode
ATmega103 Compatibility
mode
Internal SRAM Data Memory
4096
4000
External SRAM Data Memory
ATmega128
up to 64K
up to 64K
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