ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 236

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Differential Gain Channels
Changing Channel or
Reference Selection
236
ATmega128
Table 95. ADC Conversion Time
When using differential gain channels, certain aspects of the conversion need to be
taken into consideration.
Differential conversions are synchronized to the internal clock CK
ADC clock. This synchronization is done automatically by the ADC interface in such a
way that the sample-and-hold occurs at a specific edge of CK
ated by the user (i.e., all single conversions, and the first free running conversion) when
CK
clock cycles from the next prescaled clock cycle). A conversion initiated by the user
when CK
nism. In free running mode, a new conversion is initiated immediately after the previous
conversion completes, and since CK
(i.e., all but the first) free running conversions will take 14 ADC clock cycles.
The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequen-
cies may be subjected to non-linear amplification. An external low-pass filter should be
used if the input signal contains higher frequency components than the gain stage band-
width. Note that the ADC clock frequency is independent of the gain stage bandwidth
limitation. E.g. the ADC clock period may be 6 µs, allowing a channel to be sampled at
12 kSPS, regardless of the bandwidth of this channel.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
Special care should be taken when changing differential channels. Once a differential
channel has been selected, the gain stage may take as much as 125 µs to stabilize to
the new value. Thus conversions should not be started within the first 125 µs after
selecting a new differential channel. Alternatively, conversion results obtained within this
period should be discarded.
The same settling time should be observed for the first differential conversion after
changing ADC reference (by changing the REFS1:0 bits in ADMUX).
If the JTAG Interface is enabled, the function of ADC channels on PORTF7:4 is overrid-
den. Refer to Table 42, “Port F Pins Alternate Functions,” on page 80.
Condition
First conversion
Normal conversions, single ended
Normal conversions, differential
ADC2
is low will take the same amount of time as a single ended conversion (13 ADC
ADC2
is high will take 14 ADC clock cycles due to the synchronization mecha-
Sample & Hold (Cycles from
Start of Conversion)
ADC2
is high at this time, all automatically started
1.5/2.5
14.5
1.5
ADC2
ADC2
. A conversion initi-
Conversion Time
(Cycles)
equal to half the
2467M–AVR–11/04
13/14
25
13