ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 192

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

192
ATmega128
Table 78. UPMn Bits Settings
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 79. USBSn Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data
bits (character size) in a frame the Receiver and Transmitter use.
Table 80. UCSZn Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when Asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCKn).
Table 81. UCPOLn Bit Settings
UCPOLn
0
1
UCSZn2
UPMn1
0
0
0
0
1
1
1
1
0
0
1
1
Transmitted Data Changed (Output of
TxDn Pin)
Rising XCKn Edge
Falling XCKn Edge
USBSn
0
1
UCSZn1
UPMn0
0
0
1
1
0
0
1
1
0
1
0
1
Parity Mode
Disabled
(Reserved)
Enabled, Even Parity
Enabled, Odd Parity
UCSZn0
0
1
0
1
0
1
0
1
Received Data Sampled (Input on
RxDn Pin)
Falling XCKn Edge
Rising XCKn Edge
Stop Bit(s)
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
2-bits
1-bit
2467M–AVR–11/04