ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 177

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Transmission – The
USART Transmitter
Sending Frames with 5 to 8
Data Bit
2467M–AVR–11/04
More advanced initialization routines can be made that include frame format as parame-
ters, disable interrupts and so on. However, many applications use a fixed setting of the
baud and control registers, and for these types of applications the initialization code can
be placed directly in the main routine, or be combined with initialization code for other
I/O modules.
The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the
UCSRB Register. When the Transmitter is enabled, the normal port operation of the
TxD pin is overridden by the USART and given the function as the transmitter’s serial
output. The baud rate, mode of operation and frame format must be set up once before
doing any transmissions. If synchronous operation is used, the clock on the XCK pin will
be overridden and used as transmission clock.
A data transmission is initiated by loading the transmit buffer with the data to be trans-
mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The
buffered data in the transmit buffer will be moved to the Shift Register when the Shift
Register is ready to send a new frame. The Shift Register is loaded with new data if it is
in idle state (no ongoing transmission) or immediately after the last stop bit of the previ-
ous frame is transmitted. When the Shift Register is loaded with new data, it will transfer
one complete frame at the rate given by the baud register, U2X bit or by XCK depending
on mode of operation.
The following code examples show a simple USART transmit function based on polling
of the Data Register Empty (UDRE) flag. When using frames with less than eight bits,
the most significant bits written to the UDR are ignored. The USART has to be initialized
before the function can be used. For the assembly code, the data to be sent is assumed
to be stored in Register R16
Note:
Assembly Code Example
C Code Example
USART_Transmit:
void USART_Transmit( unsigned char data )
{
}
; Wait for empty transmit buffer
sbis UCSRA,UDRE
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out
ret
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE)) )
/* Put data into buffer, sends the data */
UDR = data;
1. The example code assumes that the part specific header file is included.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and
“SBI” instructions must be replaced with instructions that allow access to extended
I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
UDR,r16
;
(1)
(1)
ATmega128
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