ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 261

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Scanning the Analog
Comparator
2467M–AVR–11/04
Figure 128. Boundary-scan Cells for Oscillators and Clock Options
Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators
with XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 102. Scan Signals for the Oscillators
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in Figure 129.
The Boundary-scan cell from Figure 130 is attached to each of these signals. The sig-
nals are described in Table 103.
The Comparator need not be used for pure connectivity testing, since all analog inputs
are shared with a digital port pin as well.
Enable signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,
between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an
external clock is preferred.
the clock configuration is considered fixed for a given application. The user is advised
to scan the same clock option as to be used in the final system. The enable signals
are supported in the scan chain because the system logic can disable clock options
in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not
provided. The INTCAP fuses are not supported in the scan-chain, so the boundary
scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless
the fuse is correctly programmed.
Previous
From
Cell
ShiftDR
0
1
Scanned Clock
Line
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TOSCK
ClockDR
D
UpdateDR
Q
Next
Cell
To
D
G
Q
EXTEST
0
1
Clock Option
External Clock
External Crystal
External Ceramic Resonator
External RC
Low Freq. External Crystal
32 kHz Timer Oscillator
XTAL1/TOSC1
ENABLE
(1)(2)(3)
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
From
Cell
ShiftDR
0
1
ATmega128
ClockDR
Scanned Clock Line
when not Used
D
FF1
Q
next
cell
To
0
0
1
0
0
To System Logic
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