ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 172

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AVR USART vs. AVR UART –
Compatibility
Clock Generation
172
ATmega128
The USART is fully compatible with the AVR UART regarding:
•
•
•
•
•
However, the receive buffering has two improvements that will affect the compatibility in
some special cases:
•
•
The following control bits have changed name, but have same functionality and register
location:
•
•
The clock generation logic generates the base clock for the transmitter and receiver.
The USART supports four modes of clock operation: Normal Asynchronous, Double
Speed Asynchronous, Master Synchronous, and Slave Synchronous mode. The
UMSEL bit in USART Control and Status Register C (UCSRC) selects between asyn-
chronous and synchronous operation. Double speed (Asynchronous mode only) is
controlled by the U2X found in the UCSRA Register. When using Synchronous mode
(UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether
the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only
active when using Synchronous mode.
Figure 80 shows a block diagram of the clock generation logic.
Figure 80. Clock Generation Logic, Block Diagram
Bit locations inside all USART registers
Baud Rate Generation
Transmitter Operation
Transmit Buffer Functionality
Receiver Operation
A second buffer register has been added. The two buffer registers operate as a
circular FIFO buffer. Therefore the UDR must only be read once for each incoming
data! More important is the fact that the error flags (FE and DOR) and the ninth data
bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits
must always be read before the UDR Register is read. Otherwise the error status
will be lost since the buffer state is lost.
The receiver Shift Register can now act as a third buffer level. This is done by
allowing the received data to remain in the serial Shift Register (see Figure 79) if the
buffer registers are full, until a new start bit is detected. The USART is therefore
more resistant to Data OverRun (DOR) error conditions.
CHR9 is changed to UCSZ2
OR is changed to DOR
DDR_XCK
XCK
Pin
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
/ 2
DDR_XCK
U2X
0
1
0
1
0
1
1
0
2467M–AVR–11/04
UMSEL
txclk
rxclk