ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 310

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROG_COMMANDS ($5)
PROG_PAGELOAD ($6)
PROG_PAGEREAD ($7)
Data Registers
310
ATmega128
The AVR specific public JTAG instruction for entering programming commands via the
JTAG port. The 15-bit Programming Command Register is selected as data register.
The active states are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the
JTAG port. The 2048-bit Virtual Flash Page Load Register is selected as data register.
This is a virtual scan chain with length equal to the number of bits in one Flash page.
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state
is not used to transfer data from the Shift Register. The data are automatically trans-
ferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state
machine. This is the only active state:
•
Note:
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG
port. The 2056-bit Virtual Flash Page Read Register is selected as data register. This is
a virtual scan chain with length equal to the number of bits in one Flash page plus 8.
Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR
state is not used to transfer data to the Shift Register. The data are automatically trans-
ferred from the Flash page buffer byte by byte in the Shift-DR state by an internal state
machine. This is the only active state:
•
Note:
The data registers are selected by the JTAG instruction registers described in section
“Programming Specific JTAG Instructions” on page 308. The data registers relevant for
programming operations are:
•
•
•
•
•
Capture-DR: the result of the previous command is loaded into the data register.
Shift-DR: the data register is shifted by the TCK input, shifting out the result of the
previous command and shifting in the new command.
Update-DR: the programming command is applied to the Flash inputs.
Run-Test/Idle: one clock cycle is generated, executing the applied command.
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and
automatically loaded into the Flash page one byte at a time.
Shift-DR: Flash data are automatically read one byte at a time and shifted out on
TDO by the TCK input. The TDI input is ignored.
Reset Register
Programming Enable Register
Programming Command Register
Virtual Flash Page Load Register
Virtual Flash Page Read Register
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first
device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the
byte-wise programming algorithm must be used.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first
device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the
byte-wise programming algorithm must be used.
2467M–AVR–11/04