ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 313

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 130. JTAG Programming Instruction
Set
2467M–AVR–11/04
Instruction
1a. Chip erase
1b. Poll for chip erase complete
2a. Enter Flash Write
2b. Load Address High Byte
2c. Load Address Low Byte
2d. Load Data Low Byte
2e. Load Data High Byte
2f. Latch Data
2g. Write Flash Page
2h. Poll for Page Write complete
3a. Enter Flash Read
3b. Load Address High Byte
3c. Load Address Low Byte
3d. Read Data Low and High Byte
4a. Enter EEPROM Write
4b. Load Address High Byte
4c. Load Address Low Byte
4d. Load Data Byte
4e. Latch Data
4f. Write EEPROM Page
4g. Poll for Page Write complete
5a. Enter EEPROM Read
5b. Load Address High Byte
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
TDI sequence
0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000
0100011_00010000
0000111_aaaaaaaa
0000011_bbbbbbbb
0010011_iiiiiiii
0010111_iiiiiiii
0110111_00000000
1110111_00000000
0110111_00000000
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
0100011_00000010
0000111_aaaaaaaa
0000011_bbbbbbbb
0110010_00000000
0110110_00000000
0110111_00000000
0100011_00010001
0000111_aaaaaaaa
0000011_bbbbbbbb
0010011_iiiiiiii
0110111_00000000
1110111_00000000
0110111_00000000
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
0100011_00000011
0000111_aaaaaaaa
0110011_10000000
0110111_00000000
0110011_00000000
TDO sequence
xxxxxxx_xxxxxxxx
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xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_xxxxxxxx
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xxxxxox_xxxxxxxx
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ATmega128
Notes
(2)
(9)
(1)
(1)
(2)
(9)
low byte
high byte
(9)
(1)
(1)
(2)
(9)
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