ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 27

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pull-up and Bus-keeper
Timing
2467M–AVR–11/04
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to dis-
able the pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in “External Memory Control Reg-
ister B – XMCRB” on page 31. When enabled, the bus-keeper will ensure a defined logic
level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by
the XMEM interface.
External Memory devices have different timing requirements. To meet these require-
ments, the ATmega128 XMEM interface provides four different wait-states as shown in
Table 4. It is important to consider the timing specification of the External Memory
device before selecting the wait-state. The most important parameters are the access
time for the external memory compared to the set-up requirement of the ATmega128.
The access time for the External Memory is defined to be the time from receiving the
chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data
is stable during a read sequence (See t
144 on pages 330 - 332). The different wait-states are set up in software. As an addi-
tional feature, it is possible to divide the external memory space in two sectors with
individual wait-state settings. This makes it possible to connect two different memory
devices with different timing requirements to the same XMEM interface. For XMEM
interface timing details, please refer to Table 137 to Table 144 and Figure 156 to Figure
159 in the “External Data Memory Timing” on page 330.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and sup-
ply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
Note:
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the
next instruction accesses the RAM (internal or external).
DA7:0
A15:8
CPU
ALE
WR
RD
)
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
Address
Address
Address
LLRL
T2
+ t
RLRH
XX
XXXXX
- t
DVRH
Address
T3
in Tables 137 through Tables
Data
Data
Data
ATmega128
XXXXXXXX
T4
27