ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 278

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Entering the Boot Loader
Program
278
ATmega128
Table 108. Boot Lock Bit0 Protection Modes (Application Section)
Note:
Table 109. Boot Lock Bit1 Protection Modes (Boot Loader Section)
Note:
Entering the Boot Loader takes place by a jump or call from the application program.
This may be initiated by a trigger such as a command received via USART, or SPI inter-
face. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector
Reset is pointing to the Boot Flash start address after a reset. In this case, the Boot
Loader is started after a reset. After the application code is loaded, the program can
start executing the application code. Note that the fuses cannot be changed by the MCU
itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will
always point to the Boot Loader Reset and the fuse can only be changed through the
serial or parallel programming interface.
Table 110. Boot Reset Fuse
Note:
BLB0 mode
BLB1 mode
BOOTRST
1
2
3
4
1
2
3
4
1
0
1. “1” means unprogrammed, “0” means programmed
1. “1” means unprogrammed, “0´means programmed
1. “1” means unprogrammed, “0´means programmed
BLB02
BLB12
Reset Address
Reset Vector = Application Reset (address $0000)
Reset Vector = Boot Loader Reset (see Table 112 on page 286)
1
1
0
0
1
1
0
0
BLB01
BLB1
1
0
0
1
1
1
0
0
1
(1)
Protection
No restrictions for SPM or LPM accessing the Boot Loader
section.
SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section,
and LPM executing from the Application section is not
allowed to read from the Boot Loader section. If interrupt
vectors are placed in the Application section, interrupts are
disabled while executing from the Boot Loader section.
LPM executing from the Application section is not allowed
to read from the Boot Loader section. If interrupt vectors
are placed in the Application section, interrupts are
disabled while executing from the Boot Loader section.
Protection
No restrictions for SPM or LPM accessing the Application
section.
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and
LPM executing from the Boot Loader section is not
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
LPM executing from the Boot Loader section is not
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
(1)
(1)
2467M–AVR–11/04