ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 282

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Performing Page Erase by
SPM
Filling the Temporary Buffer
(Page Loading)
Performing a Page Write
Using the SPM Interrupt
Consideration While Updating
BLS
Prevent Reading the RWW
Section During Self-
Programming
282
ATmega128
To execute page erase, set up the address in the Z-pointer and RAMPZ, write
“X0000011” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this
operation.
•
•
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR. The content of PCWORD in the Z-register is used to address the data in the
temporary buffer. The temporary buffer will auto-erase after a page write operation or by
writing the RWWSRE bit in SPMCSR. It is also erased after a System Reset. Note that it
is not possible to write more than one time to each address without erasing the tempo-
rary buffer.
Note:
To execute page write, set up the address in the Z-pointer and RAMPZ, write
“X0000101” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE. Other bits in the Z-pointer must be written zero during this operation.
•
•
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used
instead of polling the SPMCSR Register in software. When using the SPM interrupt, the
interrupt vectors should be moved to the BLS section to avoid that an interrupt is
accessing the RWW section when it is blocked for reading. How to move the interrupts
is described in “Interrupts” on page 57.
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can
corrupt the entire Boot Loader, and further software updates might be impossible. If it is
not necessary to change the Boot Loader software itself, it is recommended to program
the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
During Self-Programming (either page erase or page write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed
during the Self-Programming operation. The RWWSB in the SPMCSR will be set as
long as the RWW section is busy. During Self-Programming the interrupt vector table
should be moved to the BLS as described in “Interrupts” on page 57, or the interrupts
must be disabled. Before addressing the RWW section after the programming is com-
pleted, the user software must clear the RWWSB by writing the RWWSRE. See “Simple
Assembly Code Example for a Boot Loader” on page 284 for an example.
Page Erase to the RWW section: The NRWW section can be read during the page
erase.
Page Erase to the NRWW section: The CPU is halted during the operation.
Page Write to the RWW section: The NRWW section can be read during the page
write.
Page Write to the NRWW section: The CPU is halted during the operation.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
will be lost.
2467M–AVR–11/04