ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 117

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Capture Pin Source
Noise Canceler
Using the Input Capture Unit
2467M–AVR–11/04
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the
low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high
byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the
ICRnH I/O location it will access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that
utilizes the ICRn Register for defining the counter’s TOP value. In these cases the
Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be
written to the ICRn Register. When writing the ICRn Register the high byte must be writ-
ten to the ICRnH I/O location before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit
Registers” on page 112.
The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alternatively use the analog comparator output as trigger source for
the Input Capture unit. The Analog Comparator is selected as trigger source by setting
the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and
Status Register (ACSR). Be aware that changing trigger source can trigger a capture.
The Input Capture flag must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are
sampled using the same technique as for the Tn pin (Figure 59 on page 142). The edge
detector is also identical. However, when the noise canceler is enabled, additional logic
is inserted before the edge detector, which increases the delay by four system clock
cycles. Note that the input of the noise canceler and edge detector is always enabled
unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to
define TOP.
An Input Capture can be triggered by software by controlling the port of the ICPn pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme.
The noise canceler input is monitored over four samples, and all four must be equal for
changing the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit
in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler intro-
duces additional four system clock cycles of delay from a change applied to the input, to
the update of the ICRn Register. The noise canceler uses the system clock and is there-
fore not affected by the prescaler.
The main challenge when using the Input Capture unit is to assign enough processor
capacity for handling the incoming events. The time between two events is critical. If the
processor has not read the captured value in the ICRn Register before the next event
occurs, the ICRn will be overwritten with a new value. In this case the result of the cap-
ture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the
interrupt handler routine as possible. Even though the Input Capture interrupt has rela-
tively high priority, the maximum interrupt response time is dependent on the maximum
number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution)
is actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed
after each capture. Changing the edge sensing must be done as early as possible after
the ICRn Register has been read. After a change of the edge, the Input Capture flag
ATmega128
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