ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet

IC AVR MCU 128K 16MHZ 5V 64TQFP

ATMEGA128-16AU

Manufacturer Part Number
ATMEGA128-16AU
Description
IC AVR MCU 128K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
High-performance, Low-power AVR
Advanced RISC Architecture
Nonvolatile Program and Data Memories
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 128K Bytes of In-System Reprogrammable Flash
– Optional Boot Code Section with Independent Lock Bits
– 4K Bytes EEPROM
– 4K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad MLF
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128
Capture Mode
and Extended Standby
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
8-bit Microcontroller
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Rev. 2467M–AVR–11/04

Related parts for ATMEGA128-16AU

ATMEGA128-16AU Summary of contents

Page 1

... TQFP and 64-pad MLF • Operating Voltages – 2.7 - 5.5V for ATmega128L – 4.5 - 5.5V for ATmega128 • Speed Grades – MHz for ATmega128L – MHz for ATmega128 ® 8-bit Microcontroller 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ...

Page 2

... The bottom pad under the MLF package should be soldered to ground. The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. 48 ...

Page 3

... PURPOSE REGISTERS ALU STATUS REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128 PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR ...

Page 4

... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128 as listed on page 70. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega128 as listed on page 74. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active ...

Page 7

... These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documentation for more details. ATmega128 7 ...

Page 8

... AVR CPU Core Introduction Architectural Overview ATmega128 8 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals and handle interrupts. Figure 3. Block Diagram of the AVR Architecture ...

Page 9

... The I/O memory space contains 64 addresses which can be accessed directly the Data Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers ...

Page 10

... General Purpose Register File ATmega128 10 The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts ...

Page 11

... X - register 7 R27 ($1B register 7 R29 ($1D register 7 R31 ($1F) In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). ATmega128 … R13 $0D R14 $0E R15 $0F R16 $10 R17 $11 … R26 $1A X-register Low Byte ...

Page 12

... Bit 0 – RAMPZ0: Extended RAM Page Z-pointer The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used ...

Page 13

... Refer to “Interrupts” on page 57 for more information. The Reset vector can also be moved to the start of the boot Flash section by programming the BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 275. ATmega128 , directly generated from the selected clock CPU ...

Page 14

... ATmega128 14 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested inter- rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. ...

Page 15

... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega128 15 ...

Page 16

... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128 Program Counter (PC bits wide, thus addressing the 64K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...

Page 17

... Register file, the next 64 location the standard I/O memory, and the next 4000 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...

Page 18

... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 4096 bytes of inter- nal data SRAM in the ATmega128 are all accessible through all these addressing modes. The Register file is described in “General Purpose Register File” on page 10. ...

Page 19

... Data RD Memory access instruction The ATmega128 contains 4K bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. “ ...

Page 20

... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...

Page 21

... The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical programming time for EEPROM access from the CPU. Table 2. EEPROM Programming Time Number of Calibrated RC Symbol EEPROM Write (from CPU) Note: 1. Uses 1 MHz clock, independent of CKSEL-fuse settings. ATmega128 (1) Oscillator Cycles Typ Programming Time 8448 8 ...

Page 22

... ATmega128 22 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish ...

Page 23

... EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low recommendation: ATmega128 23 ...

Page 24

... The I/O space definition of the ATmega128 is shown in “Register Summary” on page 364. All ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

Page 25

... The External Memory section can not be divided into sectors with different wait- state settings. • Bus-keeper is not available. • RD, WR and ALE pins are output only (Port G in ATmega128). The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus. • ...

Page 26

... Address Latch Requirements ATmega128 26 The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB. When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “ ...

Page 27

... Table important to consider the timing specification of the External Memory device before selecting the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement of the ATmega128. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...

Page 28

... ATmega128 28 Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 T1 System Clock (CLK ) CPU ALE A15:8 Prev. addr. DA7:0 Prev. data Address WR DA7:0 (XMBK = 0) Prev. data Address Prev. data DA7:0 (XMBK = 1) RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector) ...

Page 29

... Bit 7 – Res: Reserved Bit This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices. • Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit ATmega128 Address ...

Page 30

... ATmega128 possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector ...

Page 31

... To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x1100 to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to the ATmega103 compatibility mode, configuration A to the non-compatible mode. ATmega128 – ...

Page 32

... ATmega128 32 When the device is set in ATmega103 compatibility mode, the internal address space is 4,096 bytes. This implies that the first 4,096 bytes of the external memory can be accessed at addresses 0x8000 to 0x8FFF. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x1000 to 0x8FFF. ...

Page 33

... DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<<XMM1) | (1<<XMM0 0xaa; XMCRB = 0x00 0x55; } Note: 1. The example code assumes that the part specific header file is included. Care must be exercised using this option as most of the memory is masked away. ATmega128 33 ...

Page 34

... I/O Clock – clk I/O Flash Clock – clk FLASH ATmega128 34 Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...

Page 35

... The number of WDT Oscillator cycles used for each time-out is shown in Table 7. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in the “ATmega128 Typical Characteristics” on page 335. Table 7. Number of Watchdog Oscillator Cycles Typical Time-out ( ...

Page 36

... Crystal Oscillator ATmega128 36 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz crystal or a ceramic resonator may be used. The CKOPT fuse selects between two dif- ferent Oscillator Amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-to-rail swing on the output ...

Page 37

... Start-up Time from Power-down and SUT1..0 Power-save ( ( 32K CK 11 Note: 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega128 Additional Delay from Reset ( 5.0V) Recommended Usage (1) 4.1 ms Ceramic resonator, fast rising power ( Ceramic resonator, slowly rising power (2) – ...

Page 38

... External RC Oscillator ATmega128 38 For timing insensitive applications, the External RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor ...

Page 39

... This can be done by first reading the signature row by a programmer, and then store the calibration values in the Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAL Register. When OSCCAL is ATmega128 and Temperature. When this Oscillator is CC Nominal Frequency (MHz) 1 ...

Page 40

... External Clock ATmega128 40 zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency ...

Page 41

... Note: When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail. ATmega128 ...

Page 42

... If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 34 presents the different clock systems in the ATmega128, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. ...

Page 43

... Timer/Counter0 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec- ommended instead of Power-save mode because the contents of the registers in the ATmega128 and clk , while allowing the other CPU ...

Page 44

... External Crystal or resonator selected as clock source bit in ASSR is set 3. Only INT3:0 or level interrupt INT7:4 ATmega128 44 asynchronous timer should be considered undefined after wake-up in Power-save mode if AS0 is 0. This sleep mode basically halts all clocks except clk chronous modules, including Timer/Counter0 if clocked asynchronously. ...

Page 45

... Enable and Sleep Modes” on page 67 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V /2, the input buffer will use excessive power. CC ATmega128 ) and the ADC clock (clk ) are stopped, the I/O ADC ...

Page 46

... JTAG Interface and On-chip Debug System ATmega128 46 If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • ...

Page 47

... The time-out period of the delay counter is defined by the user through the CKSEL fuses. The different selections for the delay period are presented in “Clock Sources” on page 35. The ATmega128 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...

Page 48

... ATmega128 48 Figure 22. Reset Logic D Q PEN L Q Pull-up Resistor Power-On Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE RESET FILTER JTAG Reset Watchdog Register Timer Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] Table 19. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT ...

Page 49

... This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega128L and BODLEVEL=0 for ATmega128. BODLEVEL=1 is not applicable for ATmega128. A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 19 ...

Page 50

... Figure 25. External Reset During Operation CC ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection ...

Page 51

... To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. ATmega128 ...

Page 52

... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega128 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 51. ...

Page 53

... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega128 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 54

... ATmega128 the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level not possible to disable the Watchdog Timer, even with the algo- rithm described above. See “ ...

Page 55

... In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. ATmega128 55 ...

Page 56

... Safety Level 2 ATmega128 56 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence ...

Page 57

... Interrupts Interrupt Vectors in ATmega128 2467M–AVR–11/04 This section describes the specifics of the interrupt handling as performed in ATmega128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 23. Reset and Interrupt Vectors Vector Program (2) No. Address Source ...

Page 58

... ATmega128 58 Table 23. Reset and Interrupt Vectors (Continued) Vector Program (2) No. Address Source (3) 31 $003C USART1, RX (3) 32 $003E USART1, UDRE (3) 33 $0040 USART1, TX (3) 34 $0042 TWI (3) 35 $0044 SPM READY Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at reset, see “ ...

Page 59

... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega128 is: Address LabelsCode $0000 jmp RESET $0002 jmp EXT_INT0 $0004 jmp EXT_INT1 $0006 jmp EXT_INT2 $0008 jmp EXT_INT3 $000A jmp EXT_INT4 $000C jmp EXT_INT5 ...

Page 60

... ATmega128 60 ... ... ... ... When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...

Page 61

... Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 275 for details on Boot Lock bits. ATmega128 ; Enable interrupts 4 3 ...

Page 62

... ATmega128 62 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ...

Page 63

... Port Functions” on page 68. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as General Digital I/O. ATmega128 R PU Logic See Figure " ...

Page 64

... Ports as General Digital I/O Configuring the Pin ATmega128 64 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O port pin, here generically called Pxn. (1) Figure 30. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL ...

Page 65

... The maximum and minimum propagation delays are denoted t respectively. Figure 31. Synchronization when Reading an Externally Applied Pin Value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega128 I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if ext. pulled Input Yes low ...

Page 66

... ATmega128 66 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...

Page 67

... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega128 / ...

Page 68

... Unconnected pins Alternate Port Functions ATmega128 68 If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode) ...

Page 69

... The following subsections shortly describes the alternate functions for each port, and relates the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega128 Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...

Page 70

... Special Function IO Register – SFIOR Alternate Functions of Port A ATmega128 70 Bit TSM – – Read/Write R Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...

Page 71

... OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. • OC1B, Bit 6 ATmega128 PA1/AD1 PA0/AD0 SRE SRE ~(WR | ADA) • ...

Page 72

... ATmega128 72 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • ...

Page 73

... SPE • MSTR DDOV 0 0 PVOE SPE • MSTR SPE • MSTR PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT DIEOE 0 0 DIEOV SPI MSTR INPUT SPI SLAVE INPUT AIO – – ATmega128 PB6/OC1B PB5/OC1A (1) OC1B ENABLE OC1A ENABLE OC1B OC1A – – ...

Page 74

... Alternate Functions of Port C ATmega128 74 In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled ...

Page 75

... XCK1 – Port D, Bit 4 XCK1, USART1 External clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode. ATmega128 (1) PC1/A9 PC0/A8 SRE • (XMM<7) SRE • ...

Page 76

... ATmega128 76 • ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU. ...

Page 77

... When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the out- put pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega128 PD6/T1 PD5/XCK1 0 ...

Page 78

... Alternate Functions of Port E ATmega128 78 The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions Port Pin Alternate Function (1) PE7 INT7/ICP3 (External Interrupt 7 Input or Timer/Counter3 Input Capture Pin) (1) PE6 INT6/ T3 (External Interrupt 6 Input or Timer/Counter3 Clock Input) (1) INT5/OC3C (External Interrupt 5 Input or Output Compare and PWM Output C ...

Page 79

... USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega128. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega128 ...

Page 80

... Alternate Functions of Port F ATmega128 80 Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PE3/AIN1/OC3A PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE OC3B ENABLE PVOV OC3B DIEOE 0 DIEOV AIO AIN1 INPUT The Port F has an alternate function as analog input for the ADC as shown in Table 42. ...

Page 81

... AIO TDI/ADC7 INPUT ADC6 INPUT Table 44. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PF3/ADC3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC3 INPUT ATmega128 . . PF5/ADC5/TMS JTAGEN 1 JTAGEN JTAGEN 0 – TMS/ADC5 INPUT PF2/ADC2 PF1/ADC1 ...

Page 82

... Alternate Functions of Port G ATmega128 82 In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configura- tion is as follows: Table 45. Port G Pins Alternate Functions Port Pin Alternate Function ...

Page 83

... Table 47. Overriding Signals for Alternate Functions in PG0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega128 PG0/WR SRE 0 SRE 1 SRE – – 83 ...

Page 84

... Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC ATmega128 84 Bit PORTA7 PORTA6 PORTA5 Read/Write R/W ...

Page 85

... R/W R/W R/W Initial Value Bit PINE7 PINE6 PINE5 Read/Write Initial Value N/A N/A N/A Bit PORTF7 PORTF6 PORTF5 Read/Write R/W R/W R/W Initial Value ATmega128 PINC4 PINC3 PINC2 PINC1 N/A N/A N/A N PORTD4 PORTD3 PORTD2 PORTD1 R/W R/W R/W R DDD4 ...

Page 86

... Port F Data Direction Register – DDRF Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING ATmega128 86 Bit DDF7 DDF6 DDF5 Read/Write R/W R/W R/W Initial Value Bit ...

Page 87

... INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re- enabled. ATmega128 ...

Page 88

... External Interrupt Control Register B – EICRB ATmega128 88 Table 48. Interrupt Sense Control ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request Reserved 1 0 The falling edge of INTn generates asynchronously an interrupt request The rising edge of INTn generates asynchronously an interrupt request. Note: 1 ...

Page 89

... Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in inter- nal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 67 for more information. ATmega128 ...

Page 90

... Timer/Counter0 with PWM and Asynchronous Operation Overview Registers ATmega128 90 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • ...

Page 91

... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram DATA BUS count clear TCNTn Control Logic direction bottom ATmega128 ). default equal to the MCU clock, clk T0 TOVn (Int.Req.) T/C clk Tn ...

Page 92

... Output Compare Unit ATmega128 92 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk Timer/Counter clock. T0 top Signalizes that TCNT0 has reached maximum value. bottom Signalizes that TCNT0 has reached minimum value (zero). ...

Page 93

... Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. ATmega128 DATA BUS TCNTn = (8-bit Comparator ) OCFn (Int ...

Page 94

... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 94 The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the force output compare (FOC0) strobe bit in normal mode. The OC0 Register keeps its value even when changing between waveform generation modes ...

Page 95

... The timing diagram for the CTC mode is shown in Figure 38. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. Figure 38. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period 1 ATmega128 OCn Interrupt Flag Set TOV0 flag, the TOV0 (COMn1 ...

Page 96

... Fast PWM Mode ATmega128 96 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature ...

Page 97

... OC0 to toggle its logical level on each compare match (COM01:0 = 1). The waveform generated will have a maximum frequency zero. This feature is similar to the OC0 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega128 OCRn Interrupt Flag Set OCRn Update and ...

Page 98

... Phase Correct PWM Mode ATmega128 98 The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the output compare (OC0) is cleared on the compare match between TCNT0 and OCR0 while counting up, and set on the compare match while downcounting ...

Page 99

... PWM mode. Figure 41. Timer/Counter Timing Diagram, No Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 42 shows the same timing data, but with the prescaler enabled. ATmega128 f clk_I/O = ----------------- - ⋅ N 510 ) is therefore shown as T0 MAX BOTTOM BOTTOM + 1 should ...

Page 100

... ATmega128 100 Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 ...

Page 101

... Modes of oper- ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 52 and “Modes of Operation” on page 95. ATmega128 TOP BOTTOM TOP ...

Page 102

... ATmega128 102 Table 52. Waveform Generation Mode Bit Description (1) (1) WGM01 WGM00 Timer/Counter Mode (CTC0) (PWM0) Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. • ...

Page 103

... R/W Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt generate a waveform output on the OC0 pin. ATmega128 (1) Description No clock source (Timer/Counter stopped) clk /(No prescaling) T0S clk ...

Page 104

... Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter0 ATmega128 104 Bit – – – Read/Write Initial Value • Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk AS0 is written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin ...

Page 105

... Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clk ATmega128 ) again becomes active, TCNT0 will I/O 105 ...

Page 106

... Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega128 106 read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows: 1 ...

Page 107

... Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 ATmega128 10-BIT T/C PRESCALER 0 TIMER/COUNTER0 CLOCK SOURCE clk T0 ...

Page 108

... ATmega128 108 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. ...

Page 109

... I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 131. ATmega128 109 ...

Page 110

... Registers ATmega128 110 Figure 46. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTx = OCRxA = OCRxB = OCRxC ICRx TCCRxA Note: Refer to Figure 1 on page 2, Table 30 on page 71, and Table 39 on page 78 for Timer/Counter1 and 3 pin placement and description. The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Cap- ture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “ ...

Page 111

... The following bits are added to the 16-bit Timer/Counter Control Registers: • COM1C1:0 are added to TCCR1A. • FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register. • WGMn3 is added to TCCRnB. Interrupt flag and mask bits for output compare unit C are added. ATmega128 111 ...

Page 112

... Accessing 16-bit Registers ATmega128 112 The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations ...

Page 113

... I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega128 113 ...

Page 114

... Reusing the Temporary High Byte Register ATmega128 114 The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. (1) Assembly Code Example TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ...

Page 115

... CPU, independent of whether clk rides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and ATmega128 TOVn (Int.Req.) Clock Select Count ...

Page 116

... Input Capture Unit ATmega128 116 TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 121. ...

Page 117

... Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture flag ATmega128 117 ...

Page 118

... Output Compare Units ATmega128 118 (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNTn with the Output Compare Regis- ter (OCRnx) ...

Page 119

... The OCnx Register keeps its value even when changing between waveform generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. ATmega128 119 ...

Page 120

... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 120 The Compare Output mode (COMnx1:0) bits have two functions. The waveform genera- tor uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Fig- ure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting ...

Page 121

... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 51. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. ATmega128 121 ...

Page 122

... Fast PWM Mode ATmega128 122 Figure 51. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value ...

Page 123

... ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ATmega128 ( ) ...

Page 124

... Phase Correct PWM Mode ATmega128 124 ing at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA buffer Register ...

Page 125

... OCRnx Registers are written. As the third period shown in Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs ATmega128 ( ) log ...

Page 126

... Phase and Frequency Correct PWM Mode ATmega128 126 at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall- ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length ...

Page 127

... When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the TCNTn and the OCRnx. ATmega128 ( ) log ...

Page 128

... Timer/Counter Timing Diagrams ATmega128 128 As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym- metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct ...

Page 129

... PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at BOTTOM. ATmega128 OCRnx OCRnx + 1 OCRnx Value ...

Page 130

... ATmega128 130 Figure 57. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) Figure 58 shows the same timing data, but with the prescaler enabled. ...

Page 131

... WGMn3:0 bits setting. Table 58 shows the COMnx1:0 bit func- tionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 58. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnA0/COMnB0/ COMnC1 COMnC0 ATmega128 COM1B0 COM1C1 COM1C0 WGM11 R/W R/W R/W R ...

Page 132

... ATmega128 132 Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode Table 59. Compare Output Mode, Fast PWM COMnA1/COMnB1/ COMnA0/COMnB0/ COMnC0 COMnC0 Note: A special case occurs COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “ ...

Page 133

... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ATmega128 Update of (1) x TOP OCRn at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF TOP 0x01FF TOP ...

Page 134

... Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B ATmega128 134 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value Bit ICNC3 ICES3 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICPn) is filtered ...

Page 135

... Clear Timer on Compare Match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnB bits are always read as zero. • Bit 4:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when TCCRnC is written. ATmega128 – ...

Page 136

... TCNT3L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Output Compare Register 1 C – OCR1CH and OCR1CL Output Compare Register 3 A – OCR3AH and OCR3AL ATmega128 136 Bit Read/Write R/W R/W R/W ...

Page 137

... The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is per- formed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 112. ATmega128 ...

Page 138

... Timer/Counter Interrupt Mask Register – TIMSK Extended Timer/Counter Interrupt Mask Register – ETIMSK ATmega128 138 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value Note: This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • ...

Page 139

... OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out- put Compare Register B (OCR1B). ATmega128 ...

Page 140

... Extended Timer/Counter Interrupt Flag Register – ETIFR ATmega128 140 Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. ...

Page 141

... Compare Register C (OCR1C). Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. ATmega128 141 ...

Page 142

... Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega128 142 Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler mod- ule, but the Timer/Counters can have different prescaler settings. The description below applies to all of the mentioned Timer/Counters. The Timer/Counter can be clocked directly by the System Clock (by setting the CSn2 ...

Page 143

... This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a reset of this prescaler will affect all three timers. ATmega128 < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O /2 ...

Page 144

... Timer/Counter2 with PWM Overview Registers ATmega128 144 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • ...

Page 145

... Figure 62. Counter Unit Block Diagram DATA BUS count clear TCNTn Control Logic direction bottom Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Select between increment and decrement. ATmega128 ). TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top Tn 145 ...

Page 146

... Output Compare Unit ATmega128 146 clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT2 has reached maximum value. bottom Signalize that TCNT2 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or dec- ...

Page 147

... BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Out- ATmega128 DATA BUS TCNTn (8-bit Comparator ) OCFn (Int ...

Page 148

... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega128 148 put Compare (FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value ...

Page 149

... The timing diagram for the CTC mode is shown in Figure 65. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2 and then counter (TCNT2) is cleared. Figure 65. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period 1 ATmega128 OCn Interrupt Flag Set TOV 2 flag, the TOV ...

Page 150

... Fast PWM Mode ATmega128 150 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature ...

Page 151

... OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform generated will have a maximum frequency of f set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. ATmega128 OCRn Interrupt Flag Set OCRn Update and ...

Page 152

... Phase Correct PWM Mode ATmega128 152 The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM ...

Page 153

... Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. ATmega128 f clk_I/O = ----------------- - ⋅ ...

Page 154

... Timer/Counter Timing Diagrams ATmega128 154 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 68 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode ...

Page 155

... Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRn OCFn ATmega128 OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 155 ...

Page 156

... Timer/Counter Register Description Timer/Counter Control Register – TCCR2 ATmega128 156 Bit FOC2 WGM20 COM21 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode ...

Page 157

... The three clock select bits select the clock source to be used by the Timer/Counter. Table 68. Clock Select Bit Description CS22 CS21 CS20 Description clock source (Timer/Counter stopped clk I clk I clk I clk I/O ATmega128 (1) (1) /(No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) 157 ...

Page 158

... Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega128 158 Table 68. Clock Select Bit Description CS22 CS21 CS20 Description clk /1024 (From prescaler) I External clock source on T2 pin. Clock on falling edge ...

Page 159

... TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. ATmega128 R/W R/W R/W ...

Page 160

... Output Compare Modulator (OCM1C2) Overview Description ATmega128 160 The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see “ ...

Page 161

... In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 74 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on the PB7 output is equal in both periods. ATmega128 2 3 161 ...

Page 162

... Serial Peripheral Interface – SPI ATmega128 162 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega128 and peripheral devices or between several AVR devices. The ATmega128 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...

Page 163

... Table 69. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 68. (1) Table 69. SPI Pin Overrides Pin Direction, Master SPI MOSI User Defined MISO Input SCK User Defined SS User Defined ATmega128 SHIFT ENABLE Direction, Slave SPI Input User Defined Input Input 163 ...

Page 164

... ATmega128 164 Note: 1. See “Alternate Functions of Port B” on page 71 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins ...

Page 165

... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; } Note: 1. The example code assumes that the part specific header file is included. ATmega128 165 ...

Page 166

... SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega128 166 When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...

Page 167

... SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 72. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega128 Trailing edge Trailing edge Setup SPR0 SCK Frequency osc osc osc f / ...

Page 168

... CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran- teed to work lower. osc The SPI interface on the ATmega128 is also used for program memory and EEPROM downloading or uploading. See page 303 for SPI Serial Programming and verification. Bit 7 ...

Page 169

... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega128 Trailing edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...

Page 170

... Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode The ATmega128 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O registers as shown in “Register Summary” on page 364. Note that in ATmega103 compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers ...

Page 171

... In addition to the recovery units, the receiver includes a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The receiver supports the same frame formats as the Transmitter, and can detect frame error, data overrun and parity errors. ATmega128 Clock Generator OSC SYNC LOGIC ...

Page 172

... AVR USART vs. AVR UART – Compatibility Clock Generation ATmega128 172 The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • ...

Page 173

... Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from effectively doubling the transfer rate for asynchronous communication. Note however that the ATmega128 Equation for Calculating Equation for Calculating (1) ...

Page 174

... External Clock Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock ATmega128 174 receiver will in this case only use half the number of samples (reduced from for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used ...

Page 175

... The relation between the parity bit and data bits is as follows – even odd n 1 – P Parity bit using even parity even P Parity bit using odd parity odd d Data bit n of the character n ATmega128 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] ⊕ … ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 176

... USART Initialization ATmega128 176 If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The USART has to be initialized before any communication can take place. The initial- ization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage ...

Page 177

... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega128 177 ...

Page 178

... ATmega128 178 The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the data register empty interrupt is utilized, the interrupt routine writes the data into the buffer. 2467M–AVR–11/04 ...

Page 179

... This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. ATmega128 179 ...

Page 180

... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega128 180 When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro- vided that global interrupts are enabled). UDRE is cleared by writing UDR. When ...

Page 181

... I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The function simply waits for data to be present in the receive buffer by checking the RXC flag, before reading the buffer and returning the value. ATmega128 181 ...

Page 182

... Receiving Frames with 9 Data Bits ATmega128 182 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and UPE bits, which all are stored in the FIFO, will change ...

Page 183

... If parity check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 175 and “Parity Checker” on page 184. ATmega128 183 ...

Page 184

... Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception ATmega128 184 The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame ...

Page 185

... This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses ATmega128 START 6 ...

Page 186

... Asynchronous Operational Range ATmega128 186 the first stop bit of a frame. Figure 85 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 85. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = 0) ...

Page 187

... If the receiver is set up to receive frames that contain data bits, then the first stop bit indicates if the frame contains data or address information. If the receiver is set up for frames with 9 data bits, then the ninth bit (RXB8) is used for identifying address and ATmega128 Max Total Recommended Max ...

Page 188

... Using MPCM ATmega128 188 data frames. When the frame type bit (the first stop or the 9th bit) is one, the frame con- tains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU ...

Page 189

... The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. ATmega128 ...

Page 190

... USARTn Control and Status Register B – UCSRnB ATmega128 190 • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e. when the first stop bit of the next character in the receive buffer is zero. ...

Page 191

... The Receiver will generate a parity value for the incoming data and com- pare it to the UPMn0 setting mismatch is detected, the UPEn flag in UCSRnA will be set. ATmega128 ...

Page 192

... ATmega128 192 Table 78. UPMn Bits Settings UPMn1 UPMn0 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBSn Bit Settings USBSn 0 1 • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (character size frame the Receiver and Transmitter use ...

Page 193

... UBRRnL contains the eight least significant bits of the USARTn baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. ATmega128 – ...

Page 194

... UBRR = 0, Error = 0.0% ATmega128 194 For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 82. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table ...

Page 195

... ATmega128 f = 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...

Page 196

... Max 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATmega128 196 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...

Page 197

... Mbps 1.152 Mbps ATmega128 f = 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...

Page 198

... Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection ATmega128 198 • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • ...

Page 199

... REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 88. START, REPEATED START and STOP Conditions SDA SCL START ATmega128 Data Stable Data Change STOP START REPEATED START STOP 199 ...

Page 200

... Address Packet Format Data Packet Format ATmega128 200 All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation performed, otherwise a write operation should be per- formed ...

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