ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 148

IC AVR MCU 128K 16MHZ 5V 64TQFP

ATMEGA128-16AU

Manufacturer Part Number
ATMEGA128-16AU
Description
IC AVR MCU 128K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Compare Match Output
Unit
Compare Output Mode and
Waveform Generation
148
ATmega128
put Compare (FOC2) strobe bits in normal mode. The OC2 Register keeps its value
even when changing between waveform generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare
value. Changing the COM21:0 bits will take effect immediately.
The Compare Output mode (COM21:0) bits have two functions. The waveform genera-
tor uses the COM21:0 bits for defining the output compare (OC2) state at the next
compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 64
shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O
registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the gen-
eral I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits
are shown. When referring to the OC2 state, the reference is for the internal OC2 Regis-
ter, not the OC2 pin. If a System Reset occur, the OC2 Register is reset to “0”.
Figure 64. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the output compare (OC2) from the wave-
form generator if either of the COM21:0 bits are set. However, the OC2 pin direction
(input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output
before the OC2 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before
the output is enabled. Note that some COM21:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 156.
The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no
action on the OC2 Register is to be performed on the next compare match. For compare
output actions in the non-PWM modes refer to Table 65 on page 157. For fast PWM
mode, refer to Table 66 on page 157, and for phase correct PWM refer to Table 67 on
page 157.
COMn1
COMn0
FOCn
clk
I/O
Waveform
Generator
D
D
D
PORT
DDR
OCn
Q
Q
Q
1
0
2467M–AVR–11/04
OCn
Pin

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