ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 191

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USART Control and Status
Register C – UCSRnC
2467M–AVR–11/04
Writing this bit to one enables the USARTn Receiver. The Receiver will override normal
port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FEn, DORn and UPEn flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USARTn Transmitter. The Transmitter will override
normal port operation for the TxDn pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e., when the Transmit Shift Register and transmit buffer register
do not contain data to be transmitted. When disabled, the transmitter will no longer over-
ride the TxDn port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (character size) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames
with 9-data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the 9th data bit in the character to be transmitted when operating with serial
frames with 9 data bits. Must be written before writing the low bits to UDRn.
Note that this register is not available in ATmega103 compatibility mode.
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be
written to zero when UCSRnC is written.
• Bit 6 – UMSELn: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 77. UMSELn Bit Settings
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmit-
ter will automatically generate and send the parity of the transmitted data bits within
each frame. The Receiver will generate a parity value for the incoming data and com-
pare it to the UPMn0 setting. If a mismatch is detected, the UPEn flag in UCSRnA will be
set.
Bit
Read/Write
Initial Value
UMSELn
0
1
R/W
7
0
–
UMSELn
R/W
6
0
Mode
Asynchronous Operation
Synchronous Operation
UPMn1
R/W
5
0
UPMn0
R/W
4
0
USBSn
R/W
3
0
UCSZn1
R/W
2
1
UCSZn0
ATmega128
R/W
1
1
UCPOLn
R/W
0
0
UCSRnC
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