ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 283

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Setting the Boot Loader Lock
Bits by SPM
EEPROM Write Prevents
Writing to SPMCSR
Reading the Fuse and Lock
Bits from Software
2467M–AVR–11/04
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only
accessible lock bits are the Boot Lock bits that may prevent the Application and Boot
Loader section from any software update by the MCU.
See Table 108 and Table 109 for how the different settings of the Boot Loader Bits
affect the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
is recommended to load the Z-pointer with $0001 (same as used for reading the Lock
bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”
when writing the lock-bits. When programming the Lock Bits the entire Flash can be
read during the operation.
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCSR. When
an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN
bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination regis-
ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock
bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is
executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for
reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set
the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within
three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the
Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to
Table 119 on page 290 for a detailed description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Fuse High bits (FHB) will be loaded in the destination
register as shown below. Refer to Table 118 on page 290 for detailed description and
mapping of the Fuse High bits.
When reading the Extended Fuse bits, load $0002 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
Bit
R0
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
7
7
1
7
–
FHB6
FLB6
6
6
6
1
6
–
BLB12
BLB12
FHB5
FLB5
5
5
5
5
BLB11
BLB11
FHB4
FLB4
4
4
4
4
BLB02
BLB02
FLB3
FHB3
3
3
3
3
BLB01
BLB01
FHB2
FLB2
2
2
2
2
ATmega128
FHB1
FLB1
LB2
1
1
1
1
1
FHB0
FLB0
LB1
0
1
0
0
0
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