ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 115

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter Clock
Sources
Counter Unit
2467M–AVR–11/04
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the clock select logic which is controlled by the Clock Select
(CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on
c l oc k s ou r c e s a n d p re s c al er , s e e “ T i m e r/ C o u nt e r3 , Ti me r /C ou n te r 2, a n d
Timer/Counter1 Prescalers” on page 142.
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional
counter unit. Figure 47 shows a block diagram of the counter and its surroundings.
Figure 47. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High
(TCNTnH) containing the upper 8 bits of the counter, and Counter Low (TCNTnL) con-
taining the lower 8 bits. The TCNTnH Register can only be indirectly accessed by the
CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses
the high byte Temporary Register (TEMP). The Temporary Register is updated with the
TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the Temporary
Register value when TCNTnL is written. This allows the CPU to read or write the entire
16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice
that there are special cases of writing to the TCNTn Register when the counter is count-
ing that will give unpredictable results. The special cases are described in the sections
where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or dec-
remented at each Timer Clock (clk
internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source
is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, independent of whether clk
rides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode
bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and
Count
Direction
Clear
clk
TOP
BOTTOM
TCNTnH (8-bit) TCNTnL (8-bit)
T
TEMP (8-bit)
n
TCNTn (16-bit Counter)
DATA BUS
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
(8-bit)
Direction
Count
Clear
T
n
). The clk
Control Logic
TOP
T
BOTTOM
n
can be generated from an external or
T
TOVn
(Int.Req.)
n
clk
is present or not. A CPU write over-
Tn
( From Prescaler )
Clock Select
ATmega128
Detector
Edge
Tn
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