ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 214

• Manufacturer Part Number: ATMEGA128-16AU
• Description: IC AVR MCU 128K 16MHZ 5V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire, JTAG, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4096Byte
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

214
ATmega128
Figure 96. Data Transfer in Master Transmitter Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be written to one to clear the
TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START con-
dition as soon as the bus becomes free. After a START condition has been transmitted,
the TWINT flag is set by hardware, and the status code in TWSR will be $08 (See Table
88). In order to enter MT mode, SLA+W must be transmitted. This is done by writing
SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to
continue the transfer. This is accomplished by writing the following value to TWCR:
When SLA+W have been transmitted and an acknowledgment bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible sta-
tus codes in Master mode are $18, $20, or $38. The appropriate action to be taken for
each of these status codes is detailed in Table 88.
When SLA+W has been successfully transmitted, a data packet should be transmitted.
This is done by writing the data byte to TWDR. TWDR must only be written when
TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)
will be set in the TWCR Register. After updating TWDR, the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by
generating a STOP condition or a repeated START condition. A STOP condition is gen-
erated by writing the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
TWINT
TWINT
TWINT
TWINT
TWINT
TRANSMITTER
Device 1
1
1
1
1
1
MASTER
TWEA
TWEA
TWEA
TWEA
TWEA
X
X
X
X
X
Device 2
RECEIVER
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
0
1
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
TWSTO
0
0
0
1
0
........
TWWC
TWWC
TWWC
TWWC
TWWC
X
X
X
X
X
Device n
TWEN
TWEN
TWEN
TWEN
TWEN
V
1
1
1
1
1
CC
R1
–
0
–
0
–
0
–
0
–
0
2467M–AVR–11/04
R2
TWIE
TWIE
TWIE
TWIE
TWIE
X
X
X
X
X