EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 842

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Using MultiVolt I/O Pins
Using MultiVolt
I/O Pins
14–2
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Table 14–1. Cyclone MultiVolt I/O Support
1.5-V
1.8-V
2.5-V
3.3-V
The PCI clamping diode must be disabled to drive an input with voltages higher than V
When V
When V
When V
than expected.
When V
Cyclone devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.
When V
When V
V
CCIO
Table
(V)
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
14–1:
= 1.5-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is expected.
= 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs.
= 3.3-V and a 2.5-V input signal feeds an input pin, the V
= 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.
= 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.
= 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs.
1.5-V
v
Cyclone FPGAs require a 1.5-V V
I/O supply voltage level (V
clock, I/O, and JTAG pins, are 3.3-V tolerant before and after V
V
When V
logic levels. The output pins can be made 1.8-V, 2.5-V, or 3.3-V compatible
by using open-drain outputs pulled up with external resistors. You can
use external resistors to pull open-drain outputs up with a 1.8-V, 2.5-V, or
3.3-V V
1.8-V
CCIO
v
v
Input Signal
are powered.
CCIO
CCIO
2.5-V
v
v
v
v
.
(2)
(4)
Table 14–1
is connected to 1.5-V, the output is compatible with 1.5-V
Note (1)
v
3.3-V
v
v
v
(2)
summarizes Cyclone MultiVolt I/O support.
5.0-V
v
CCIO
(6)
). All pins, including dedicated inputs,
CCINT
1.5-V
v
v
v
v
CCIO
(3)
(5)
(7)
and a 3.3-V, 2.5-V, 1.8-V, or 1.5-V
supply current will be slightly larger
v
v
1.8-V
v
(5)
(7)
Output Signal
2.5-V
v
v
CCIO
(7)
.
Altera Corporation
3.3-V
v
January 2005
CCINT
5.0-V
v
and
(8)