EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 442

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Stratix & Stratix GX I/O Standards
4–14
Stratix Device Handbook, Volume 2
PCML standard is similar to LVPECL, but PCML has a reduced voltage
swing, which allows for a faster switching time and lower power
consumption. The PCML standard uses open drain outputs and requires
a differential output signal. See
termination. Stratix and Stratix GX devices support both input and
output levels.
Additionally, Stratix GX devices support 1.5-V PCML as described in the
Stratix GX Device Handbook, Volume 1.
Figure 4–16. PCML Termination
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential high-
speed, high-performance I/O interface standard requiring a 2.5-V V
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. The HyperTransport
technology standard does not require an input reference voltage.
However, it does require a 100-
signals at the input buffer. See
technology termination. Stratix and Stratix GX devices support both
input and output levels.
Figure 4–17. HyperTransport Technology Termination
V
Output Buffer
TT
50 Ω
Output Buffer
50 Ω
Z = 50 Ω
Z = 50 Ω
Figure 4–17
Z = 50 Ω
Z = 50 Ω
Figure 4–16
termination resistor between the two
100 Ω
50 Ω
for details on HyperTransport
Input Buffer
for details on PCML
50 Ω
Altera Corporation
Input Buffer
June 2006
CCIO
.