EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 382

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Using TriMatrix Memory
Figure 2–7. True Dual-Port Timing Waveforms
2–14
Stratix Device Handbook, Volume 2
A_asynch_data_out
B_asynch_data_out
B_synch_data_out
A_synch_data_out
A_address
B_address
A_wren
A_data_in
B_wren
B_clk
A_clk
doutn-2
din-1
doutn-1
an-1
bn
din-2
din-1
an
din
Implementing Shift-Register Mode
Embedded memory block configurations can implement shift registers
for digital signal processing (DSP) applications, such as finite impulse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP applications require local data storage, traditionally
implemented with standard flip-flops that can quickly consume many
logic cells for large shift registers. A more efficient alternative is to use
embedded memory as a shift register block, which saves logic cell and
routing resources and provides a more efficient implementation.
The size of a (w
width (w), the length of the taps (m), and the number of taps (n). The size
of a (w
number of memory bits in the respective block: 576 bits for the M512
block and 4,608 bits for the M4K block. In addition, the size of w
be less than or equal to the maximum width of the respective block: 18
bits for the M512 block and 36 bits for the M4K block. If a larger shift
register is required, the memory blocks can be cascaded together.
1
doutn-1
din-1
doutn
din
a0
b0
M-RAM blocks do not support the shift-register mode.
m
n) shift register must be less than or equal to the maximum
din
dout0
m
a1
doutn
n) shift register is determined by the input data
dout0
dout0
dout1
a2
b1
dout1
dout2
a3
dout0
dout2
dout1
dout3
din4
a4
b2
dout3
Altera Corporation
din4
din5
a5
dout1
July 2005
din4
dout2
din5
n must
b3
din6
a6