EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 431

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B
The 3.3-V low voltage complementary metal oxide semiconductor
(LVCMOS) I/O standard is a general-purpose, single-ended standard
used for 3.3-V applications. The LVCMOS standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (–0.5 V V
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVCMOS operation.
2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This
standard defines the DC interface parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
2.5-V devices. The input and output voltage ranges are:
■
■
Stratix and Stratix GX devices support both input and output levels for
2.5-V LVTTL operation.
2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This
standard defines the DC interface parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
2.5-V parts. The input and output voltage ranges are:
■
■
The 2.5-V normal range input standards specify an input voltage
range of – 0.3 V
The normal range minimum high-level output voltage requirement
(V
The 2.5-V normal range input standards specify an input voltage
range of – 0.5 V V
The normal range minimum V
OH
) is 2.1 V.
I
Selectable I/O Standards in Stratix & Stratix GX Devices
3.8 V). The output buffer drives to the rail to meet the
V
I
I
3.0 V.
3.0 V.
OH
requirement is 2.1 V.
Stratix Device Handbook, Volume 2
4–3