EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 325

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
f
Phase Delay
The Quartus II software automatically sets the phase taps and counter
settings according to the phase shift entry. You enter a desired phase shift
and the Quartus II software automatically sets the closest setting
achievable. This type of phase shift is not reconfigurable during system
operation. For phase shifting, enter a phase shift (in degrees or time units)
for each PLL clock output port or for all outputs together in one shift.
You can select phase-shifting values in time units with a resolution of
156.25 to 416.66 ps. This resolution is a function of frequency input and
the multiplication and division factors (that is, it is a function of the VCO
period), with the finest step being equal to an eighth ( 0.125) of the VCO
period. Each clock output counter can choose a different phase of the
VCO period from up to eight taps for individual fine-step selection. Also,
each clock output counter can use a unique initial count setting to achieve
individual coarse-shift selection in steps of one VCO period. The
combination of coarse and fine shifts allows phase shifting for the entire
input clock period.
The equation to determine the precision of the phase shifting in degrees
is: 45
45 , and smaller steps are possible depending on the multiplication and
division ratio necessary on the output counter port.
This type of phase shift provides the highest precision since it is the least
sensitive to process, supply, and temperature variation.
Lock Detect
The lock output indicates that there is a stable clock output signal in
phase with the reference clock. Without any additional circuitry, the lock
signal may toggle as the PLL begins tracking the reference clock. You may
need to gate the lock signal for use as a system control. The lock signal
from the locked port can drive the logic array or an output pin.
Whenever the PLL loses lock for any reason (be it excessive inclk jitter,
clock switchover, PLL reconfiguration, power supply noise, etc.), the PLL
must be reset with the areset signal to guarantee correct phase
relationship between the PLL output clocks. If the phase relationship
between the input clock versus output clock, and between different
output clocks from the PLL is not important in your design, the PLL need
not be reset.
See the Stratix FPGA Errata Sheet for more information on implementing
the gated lock signal in your design.
post-scale counter value. Therefore, the maximum step size is
General-Purpose PLLs in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
1–15