EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 369

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
TriMatrix
Memory
Altera Corporation
July 2005
S52003-3.3
f
Stratix and Stratix GX devices feature the TriMatrix™ memory
structure, composed of three sizes of embedded RAM blocks. TriMatrix
memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit
M-RAM blocks, each of which is configurable to support a wide range of
features. Offering up to 10 Mbits of RAM and up to 12 terabits per second
of device memory bandwidth, the TriMatrix memory structure makes the
Stratix and Stratix GX families ideal for memory-intensive applications.
TriMatrix memory structures can implement a wide variety of complex
memory functions. For example, use the small M512 blocks for first-in
first-out (FIFO) functions and clock domain buffering where memory
bandwidth is critical. The M4K blocks are an ideal size for applications
requiring medium-sized memory, such as asynchronous transfer mode
(ATM) cell processing. M-RAM blocks enhance programmable logic
device (PLD) memory capabilities for large buffering applications, such
as internet protocol (IP) packet buffering and system cache.
TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift-register, ROM, and FIFO mode. The
TriMatrix memory architecture also includes advanced features and
capabilities, such as byte enable support, parity-bit support, and mixed-
port width support. This chapter describes the various TriMatrix memory
modes and features.
Table 2–1
TriMatrix memory.
For more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
summarizes the features supported by the three sizes of
Stratix & Stratix GX Devices
2. TriMatrix Embedded
Memory Blocks in
2–1