EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 661

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 8–13. Stratix & Stratix GX XGMII Input Implementation (One Channel)
Altera Corporation
July 2005
Transmitter
MAC
DATA
CLK
f
MAC_TXCLK
156.25 MHz
312.5 Mbps
TX_D[0]
Stratix and Stratix GX devices contain up to four enhanced PLLs. These
PLLs provide features such as clock switchover, spread-spectrum
clocking, programmable bandwidth, phase and delay control, and PLL
reconfiguration. Since the maximum clock rate is 156.25 MHz, you can
use a fast or enhanced PLL for both the XGMII output and input blocks.
For more information about fast PLLs, see the Stratix Device Family Data
Sheet section of the Stratix Device Handbook, Volume 1 or the Stratix GX
Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
With this implementation for the XGMII output and input blocks, the
number of XGMII cores per device corresponds to the number of PLLs
each Stratix and Stratix GX device contains.
number of 1.5-V HSTL I/O pins, PLLs, and XGMII cores that are
supported in each Stratix and Stratix GX device. Each core requires 72 1.5-
DDR Input Circuitry
D0,D2,D4,D6
D1,D3,D5,D7
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
DFF
DFF
Latch
PLL
÷4
156.25 MHz
Stratix & Stratix GX PCS Input
39.0625 MHz
Register
Register
Shift
Shift
4
4
Stratix Device Handbook, Volume 2
8
Tables 8–6
DFF
8
and
DATA
CLK
Logic Array
Stratix GX
Stratix &
8–7
show the
8–17