EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 523

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Software
Support
Altera Corporation
July 2005
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This section provides information on using the Quartus II software to
create Stratix designs with LVDS transmitters or receivers. You can use
the altlvds megafunction in the Quartus II software to implement the
SERDES circuitry. You must bypass the SERDES circuitry in
mode designs and use the altddio megafunction to implement the
deserialization instead. You can use either the logic array or the M512
RAM blocks closest to the differential pins for deserialization in SERDES
bypass mode.
Differential Pins in Stratix
Stratix device differential pins are located in I/O banks 1, 2, 5, and 6 (see
Figure 5–1 on page
differential receiver pin pairs. You can use each differential transmitter
pin pair as either a differential data pin pair or a differential clock pin pair
because Stratix devices do not have dedicated LVDS tx_outclock pin
pairs. The differential receiver pin pairs can only function as differential
data pin pairs. You can use these differential pins as regular user I/O pins
when not used as differential pins. When using differential signaling in
an I/O bank, you cannot place non-differential output or bidirectional
pads within five I/O pads of either side of the differential pins to avoid a
decrease in performance on the LVDS signals.
You only need to make assignments to the positive pin of the pin-pair.
The Quartus II software automatically reserves and makes the same
assignment to the negative pin. If you do not assign any differential I/O
standard to the differential pins, the Quartus II software sets them as
LVDS differential pins during fitting, if the design uses the SERDES
circuitry. Additionally, if you bypass the SERDES circuitry, you can still
use the differential pins by assigning a differential I/O standard to the
pins in the Quartus II software. However, when you bypass the SERDES
circuitry in the
I/O standard to the associated pins in the Assignment Organizer. For
more information on how to use the Assignment Organizer, see the
Quartus II On-Line Help.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins as the TCCS value increases.
Limit vias because they cause discontinuities.
Use the common bypass capacitor values such as 0.001 µF, 0.01 µF,
and 0.1 µF to decouple the fast PLL power and ground planes.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
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1 and
5–2). Each bank has differential transmitter and
High-Speed Differential I/O Interfaces in Stratix Devices
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2 mode, you must assign the correct differential
Stratix Device Handbook, Volume 2
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1 and
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5–51
2