EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 588

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Finite Impulse Response (FIR) Filters
7–10
Stratix Device Handbook, Volume 2
f
When the coefficients are loaded in parallel, they can be fed directly from
memory elements or any other muxing scheme. This facilitates the
implementation of an adaptive (variable) filter.
Further, if the user wants to implement the shift register chains external
to the DSP block, this can be done by using the altshift_taps
megafunction. In this case, the coefficient and data shifting is done
external to the DSP block. The DSP block is only used to implement the
multiplications and the additions.
Parallel vs. Serial Implementation
The fastest implementations are fully parallel, but consume more logic
resources than serial implementations. To trade-off performance for logic
resources, implement a serial scheme with a specified number of taps. To
facilitate this, Altera provides the FIR Compiler core through its
MegaCore program. The FIR Compiler is an easy-to-use, fully-integrated
graphical user interface (GUI) based FIR filter design software.
For more information on the FIR Compiler MegaCore, visit the Altera
web site at www.altera.com and search for “FIR compiler” in the
“Intellectual Property” page.
It is important to note that the four-multipliers adder mode allows a DSP
block to be configured for parallel or serial input. When it is configured
for parallel input, as shown in
coefficients can be loaded directly without the need for shiftin/shiftout
chains between adjacent registers in the DSP block. When the DSP block
is configured for serial input, as shown in
chains create a register cascade both within the DSP block and also
between adjacent DSP blocks.
Figure
7–6, the data input and the
Figure
7–5, the shiftin/shiftout
Altera Corporation
September 2004