EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 733

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 11–5. PS Configuration Circuit with a Download Cable
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
Pin 6 of the header is a V
V
CCIO
Figure
. This pin is a no-connect pin for the ByteBlasterMV header.
(2)
V CC (1)
10 kΩ
11–5:
10 kΩ
V CC (1)
(2)
(2)
V CC (1)
IO
10 kΩ
reference voltage for the MasterBlaster output driver. V
You can use programming hardware to configure multiple Stratix and
Stratix GX devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. All other configuration pins are connected
to each device in the chain.
Because all CONF_DONE pins are tied together, all devices in the chain
initialize and enter user mode at the same time. In addition, because the
nSTATUS pins are tied together, the entire chain halts configuration if any
device detects an error. In this situation, the Quartus II software must
restart configuration; the Auto-Restart Configuration on Frame Error
option does not affect the configuration cycle.
Figure 11–6
devices with a MasterBlaster or ByteBlasterMV cable.
GND
V CC
MSEL2
MSEL1
MSEL0
nCE
DCLK
DATA0
nCONFIG
Stratix GX Device
Stratix or
shows how to configure multiple Stratix and Stratix GX
CONF_DONE
nSTATUS
nCEO
N.C.
V CC (1)
10 kΩ
Configuring Stratix & Stratix GX Devices
V CC (1)
Stratix Device Handbook, Volume 2
10 kΩ
Pin 1
IO
10-Pin Male Header
should match the device’s
Download Cable
Shield
GND
(PS Mode)
V CC
VIO (3)
GND
11–15