EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 347

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
CLK0p/n
CLK1p/n
CLK2p/n
CLK3p/n
CLK8p/n
CLK9p/n
CLK10p/n
CLK11p/n
FPLL7CLKp/n
FPLL8CLKp/n
FPLL9CLKp/n
FPLL10CLKp/n
PLLENABLE
VCCA_PLL1
Table 1–13. Fast PLL Pins (Part 1 of 3)
Pin
resynchronizes to its input clock as it relocks. If the target VCO frequency
is below this nominal frequency, then the output frequency starts at a
higher value then desired as it locks.
The pfdena signals control the PFD output with a programmable gate. If
you disable the PFD, the VCO operates at its last set value of control
voltage and frequency with some long-term drift to a lower frequency.
The system continues running when the PLL goes out of lock or the input
clock disables. By maintaining the last locked frequency, the system has
time to store its current settings before shutting down.
If the PLL loses lock for any reason (for example, because of excessive
inclk jitter, clock switchover, PLL reconfiguration, or power supply
noise), the PLL must be reset with the areset signal to guarantee correct
phase relationship between the PLL output clocks. If the phase
relationship between the input clock and the output clock and between
different output clocks from the PLL is not important in your design, it is
not necessary to reset the PLL.
Pins
Table 1–13
For inclk port connections to pins see
Single-ended or differential pins that can drive the inclk port for PLL 1 or 7.
Single-ended or differential pins that can drive the inclk port for PLL 1.
Single-ended or differential pins that can drive the inclk port for PLL 2 or 8.
Single-ended or differential pins that can drive the inclk port for PLL 2.
Single-ended or differential pins that can drive the inclk port for PLL 3 or 9.
Single-ended or differential pins that can drive the inclk port for PLL 3.
Single-ended or differential pins that can drive the inclk port for PLL 4 or 10.
Single-ended or differential pins that can drive the inclk port for PLL 4.
Single-ended or differential pins that can drive the inclk port for PLL 7.
Single-ended or differential pins that can drive the inclk port for PLL 8.
Single-ended or differential pins that can drive the inclk port for PLL 9.
Single-ended or differential pins that can drive the inclk port for PLL 10.
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not
use this pin, connect it to ground.
Analog power for PLL 1. Connect this pin to 1.5 V, even if the PLL is not used.
shows the physical pins and their purpose for the Fast PLLs.
General-Purpose PLLs in Stratix & Stratix GX Devices
Description
“Clocking” on page
Stratix Device Handbook, Volume 2
1–39.
(1)
(1)
(1)
(1)
(1)
1–37
(1)