EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 720

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Device Configuration Overview
Device
Configuration
Overview
Figure 11–1. Stratix & Stratix GX Configuration Cycle
Notes to
(1)
(2)
(3)
(4)
(5)
11–2
Stratix Device Handbook, Volume 2
CONF_DONE (1)
User I/O Pins (2)
INIT_DONE (3)
During initial power up and configuration, CONF_DONE is low. After configuration, CONF_DONE goes high. If the
device is reconfigured, CONF_DONE goes low after nCONFIG is driven low.
User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistor
on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform
the function assigned in the user’s design.
If the INIT_DONE pin is used, it will be high because of an external 10 k
and during the beginning of configuration. Once the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin will go low.
DCLK should not be left floating. It should be driven high or low.
DATA0 should not be left floating. It should be driven high or low.
Figure
nCONFIG
nSTATUS
MODE
DCLK
DATA
11–1:
f
High-Z
Configuration
■
For more information on setting device configuration options or
generating configuration files, see the Software Setting chapter in
Volume 2 of the Configuration Handbook.
During device operation, the FPGA stores configuration data in SRAM
cells. Because SRAM memory is volatile, you must load the SRAM cells
with the configuration data each time the device powers up. After
configuration, the device must initialize its registers and I/O pins. After
initialization, the device enters user mode.
the device during the configuration, initialization, and user mode.
You can load the configuration data for the Stratix or Stratix GX device
using a passive configuration scheme. When using any passive
configuration scheme, the Stratix or Stratix GX device is incorporated into
a system with an intelligent host, such as a microprocessor, that controls
the configuration process. The host supplies configuration data from a
storage device (e.g., a hard disk, RAM, or other system memory). When
using passive configuration, you can change the target device’s
High-Z
D0
The Remote System Configuration with Stratix & Stratix GX Devices
chapter
D1
D2
D3
D(N – 1)
Configuration
DN
High-Z
Initialization
resistor pull-up when nCONFIG is low
Figure 11–1
shows the state of
Altera Corporation
User I/O
User
(4)
(5)
July 2005