EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 648

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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10-Gigabit Ethernet
Figure 8–2. 10-Gigabit Ethernet Block Diagram
Notes to
(1)
(2)
(3)
8–4
Stratix Device Handbook, Volume 2
PHY
The reconciliation sublayer (RS) interfaces the serial MAC data stream and the parallel data of XGMII.
The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data
conversion between XGMII and XAUI.
The WAN interface sublayer (WIS) implements the OC-192 framing and scrambling functions.
Figure
Interface directly covered in this
application note
Interface indirectly covered in this
application note
Can be implemented in Altera PLDs
10GBASE-X
8–2:
PMD
PCS
PMA
8B/10B
MDI
10GBASE-R
XGXS (2)
RS (1)
XGXS
MAC
PMD
PCS
PMA
644.5 Mbps LVDS)
XSBI (16 Bits at
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
XAUI (4 Bits at 3.125 Gbps PCML)
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
64b/66b
8b/10b
MDI
8b/10b
10GBASE-W
WIS (3)
PMD
PMA
PCS
Altera Corporation
622.08 Mbps LVDS)
XSBI (16 Bits at
OC-192 Framing
July 2005
64b/66b

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