EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 660

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Interfaces
Figure 8–12. Stratix & Stratix GX XGMII Output Implementation (One Channel)
8–16
Stratix Device Handbook, Volume 2
Stratix & Stratix GX PCS Output
Logic Array
Stratix GX
Stratix &
DATA
CLK
D0,D2,D4,D6
D1,D3,D5,D7
8
PLL
Figure 8–13
From the receiver side, the DDR data is captured from the MAC to the
Stratix and Stratix GX PCS DDR input circuitry. The serial data is
separated into two individual data streams with the even bits routed to
the top register and odd bits routed to the bottom register. The DDR input
circuitry produces two output data streams that go into the shift registers.
From the shift registers, the data is deserialized using the clock from the
MAC, combining into an 8-bit word. This parallel data goes to a register
that is clocked by the divide-by-4 clock from the PLL. This data and clock
go to the Stratix and Stratix GX core. This implementation shows only one
channel, but can be duplicated to include all 32 bits of the TX_D signal and
all 4 bits of the TX_C signal.
×4
4
4
39.0625 MHz
156.25 MHz
Register
Register
Shift
Shift
DDR Output Circuitry
shows one channel of the input half of the XGMII interface.
DFF
DFF
MAC_RXCLK
156.25 MHz
312.5 Mbps
RX_D[0]
Altera Corporation
DATA
CLK
Receiver
MAC
July 2005