EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 513

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget
Altera Corporation
July 2005
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Clock
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
TPPos (min)
Bit n
TPPos (max)
Bit n
TCCS
T
SWBEGIN
RSKM
RSKM
t
SW
Bit n
(min)
Time Unit Interval (TUI)
Clock Placement
High-Speed Differential I/O Interfaces in Stratix Devices
Window (SW)
Sampling
Sampling
Falling Edge
Window
T
SWEND
Internal
TUI
Clock
t
SW
Bit n
(max)
Stratix Device Handbook, Volume 2
RSKM
RSKM
TCCS
TPPos (min)
Bit n + 1
TPPos (max)
Bit n + 1
TCCS
2
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