EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 512

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Source-Synchronous Timing Budget
Figure 5–26. Output Timing Waveform
Note to
(1)
5–40
Stratix Device Handbook, Volume 2
Output Clock
(Differential
Signal)
Output Data
TPPos0 (max)
TPPos1 (max)
TPPos2 (max)
TPPos3 (max)
TPPos4 (max)
TPPos5 (max)
TPPos6 (max)
TPPos7 (max)
TPPos0 (min)
TPPos1 (min)
TPPos2 (min)
TPPos3 (min)
TPPos4 (min)
TPPos5 (min)
TPPos6 (min)
TPPos7 (min)
The timing specifications are referenced at a 250-mV differential voltage.
Figure
5–26:
Previous Cycle
bit 0
Output Timing
The output timing waveform in
between the output clock and the serial output data stream.
Receiver Skew Margin
Change in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, a receiver's inherent setup and hold,
and internal skew, reduces the sampling window for the receiver. The
timing margin between receiver’s clock input and the data input
sampling window is known as RSKM.
relationship between the parameter and the receiver’s sampling window.
bit 1
MSB
bit 2
Note (1)
bit 3
bit 4
bit 5
Current Cycle
Figure 5–26
bit 6
Figure 5–27
illustrates the relationship
bit 7
illustrates the
Altera Corporation
LSB
July 2005
Cycle
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