EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 668

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Characteristics for XSBI, XGMII & XAUI
8–24
Stratix Device Handbook, Volume 2
Note to
(1)
V
V
V
V
V
V
V
I
V
V
I
I
O
Table 8–11. DC Specifications for Stratix & Stratix GX Devices (1.5-V HSTL Class I)
CCIO
REF
TT
IH
IL
IH
IL
OH
OL
Symbol
(DC)
(AC)
(DC)
(AC)
Drive strength is programmable according to values shown in the Stratix Device Family Data Sheet section of the
Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
Table
8–11:
I/O supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
Input pin leakage current
High-level output voltage
Low-level output voltage
Output leakage current
(when output is high Z)
Parameter
Table 8–11
(1.5-V HSTL Class I).
10-Gigabit Ethernet MAC Core
As an Altera Megafunction Partners Program (AMPP
MorethanIP provides a 10-Gigabit Ethernet MAC core for Altera
customers. MorethanIP’s 10-Gigabit Ethernet MAC core implements the
RS, the MAC layer, and user-programmable FIFO buffers for clock and
data decoupling.
Core Features
MorethanIP’s 10-Gigabit Ethernet MAC core provides the following
features:
■
■
Includes automatic pause frame generation (per IEEE 802.3 31) with
user-programmable pause quanta and pause-frame termination
Includes a programmable 48-bit MAC address with a promiscuous
mode option, and a programmable Ethernet frame length that
supports IEEE 802.1Q VLAN-tagged frames or jumbo Ethernet
frames
lists the DC specifications for Stratix and Stratix GX devices
0 < V
GND V
I
Conditions
OH
I
OL
V
= –8 mA
IN
= 8 mA
CCIO
< V
OUT
CCIO
V
V
V
Minimum
CCIO
REF
REF
0.68
–0.3
–10
–10
1.4
0.7
+ 0.1
+ 0.2
– 0.4
Typical
0.75
0.75
1.5
Note (1)
Maximum
V
V
SM
REF
REF
Altera Corporation
) member,
1.6
0.9
0.8
0.4
10
10
– 0.1
– 0.2
July 2005
Units
V
V
V
V
V
V
V
V
V
A
A