EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 376

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Using TriMatrix Memory
Figure 2–3. Single-Port Timing Waveforms
2–8
Stratix Device Handbook, Volume 2
asynch_data_out
synch_data_out
in clock
address
data_in
wren
din-1
an-1
din-2
din-1
an
din
In the single-port RAM configuration, the outputs can only be in
read-during-write mode, which means that during the write operation,
data written to the RAM flows through to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle it was written on. For more information about
read-during-write mode, see
Address” on page
Figure 2–3
single-port mode.
Implementing Simple Dual-Port Mode
Simple dual-port memory supports a simultaneous read and write.
Figure 2–4
TriMatrix memory. All memory block types support this configuration.
Figure 2–4. Simple Dual-Port Memory
Note to
(1)
din-1
Simple dual-port RAM supports read/write clock mode in addition to the
input/output clock mode shown.
din
Dual-Port Memory
a0
Figure
shows timing waveforms for read and write operations in
shows the simple dual-port memory configuration for
2–4:
din
dout0
a1
2–25.
data[ ]
wraddress[ ]
wren
inclocken
inaclr
inclock
dout0
dout1
a2
“Read-During-Write Operation at the Same
dout1
Note (1)
dout2
a3
dout2
dout3
rdaddress[ ]
outclocken
din4
outclock
a4
outaclr
rden
q[ ]
dout3
Altera Corporation
din4
din5
a5
July 2005
din4
din5
din6
a6