EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 777

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
Table 11–16. Optional Configuration Pins
Pin Name
N/A if option is
on. I/O if option
is off.
N/A if option is
on. I/O if option
is off.
N/A if option is
on. I/O if option
is off.
N/A if option is
on. I/O if option
is off.
User Mode
Table 11–16
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-ups.
Input
Output open-
drain
Input
Input
Pin Type
describes the optional configuration pins. If these optional
Optional user-supplied clock input. Synchronizes the
initialization of one or more devices. This pin is enabled by
turning on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software.
Status pin. Can be used to indicate when the device has
initialized and is in user mode. When
during the beginning of configuration, the
tri-stated and pulled high due to an external 10-k pull-up.
Once the option bit to enable
into the device (during the first frame of configuration data),
the
complete, the
and the FPGA enters user mode. Thus, the monitoring
circuitry must be able to detect a low-to-high transition. This
pin is enabled by turning on the Enable INIT_DONE output
option in the Quartus II software.
Optional pin that allows the user to override all tri-states on
the device. When this pin is driven low, all I/Os are tri-stated.
When this pin is driven high, all I/Os behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
Optional pin that allows you to override all clears on all
device registers. When this pin is driven low, all registers are
cleared. When this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
INIT_DONE
INIT_DONE
Configuring Stratix & Stratix GX Devices
pin goes low. When initialization is
Stratix Device Handbook, Volume 2
Description
pin is released and pulled high
INIT_DONE
nCONFIG
INIT_DONE
is programmed
is low and
11–59
pin is