EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 561

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
accum_sload[1..0] signals to clear the accumulator asynchronously.
This action is not the same as resetting the output registers. You can clear
the accumulation and begin a new one without losing any clock cycles.
The overflow signal goes high on the positive edge of the clock when
the accumulator overflows or underflows. In the next clock cycle,
however, the overflow signal resets to zero even though an overflow (or
underflow) occurred in the previous clock cycle. Use a latch to preserve
the overflow condition indefinitely (until the latch is cleared).
Adder/Subtractor
The addnsub[1..0] signals select addition or subtraction: high for
addition and low for subtraction. You can control the addnsub[1..0]
signals using external logic; therefore, the first-level block can switch
from an adder to a subtractor dynamically, simply by changing the
addnsub[1..0] signals. If the first stage is configured as a subtractor,
the output is A - B and C - D.
The adder/subtractor also uses two signals, signa and signb, like the
multiplier block. These signals indicate the sign representation of both
operands together. You can register the signals with a latency of 1 or 2
clock cycles.
Summation Block
The output from the adder/subtractor feeds to an optional summation
block, which is an adder block that sums the outputs of the
adder/subtractor. The summation block is important in applications
such as FIR filters.
Output Select Multiplexer
The outputs from the various elements of the adder/output block are
routed through an output select multiplexer. Based on the DSP block
operational mode, the outputs of the multiplier block,
adder/subtractor/accumulator, or summation block feed straight to the
output, bypassing the remaining blocks in the DSP block.
1
Output Registers
You can use the output registers to register the DSP block output. Like the
input registers, the output registers are controlled by the four
clock[3..0], aclr[3..0], and ena[3..0] signals. You can use the
output registers in any DSP block operational mode.
The output select multiplier configuration is configured
automatically by software.
DSP Blocks in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
6–11