EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 610

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Finite Impulse Response (FIR) Filters
7–32
Stratix Device Handbook, Volume 2
where:
In complex representation, this equals:
The overall real channel output is obtained by adding the real channel
outputs of all the multipliers. Similarly, the overall imaginary channel
output is obtained by adding the imaginary channel outputs of all the
multipliers.
Figure 7–18. Complex FIR Filter Block Diagram
Complex FIR Filter Implementation
Complex filters can be easily implemented in Stratix devices with the DSP
blocks configured in the two-multipliers adder mode. One DSP block can
implement a 2-tap complex FIR filter with 9-bit inputs, or a single tap
complex FIR filter with 18-bit inputs. DSP blocks can be cascaded to
implement complex filters with more taps.
1
x
x
h
h
y
y
y
y
y
real
imag
real
imag
real
imag
real
imag
real
is the real input signal
is the real filter coefficients
is the real output signal
The two-multipliers adder mode has two adders, each adding
the outputs of two multipliers. One of the adders is configured
as a subtractor.
is the imaginary input signal
is the imaginary filter coefficients
is the imaginary output signal
+
=
=
jy
x
imag
x
real
real
x imag
x real
=
h
h
real
x
imag
real
–
+
+
x
imag
h
jx
real
imag
h real
Complex
FIR filter
h
x
imag
imag
h imag
h
real
+
jh
imag
y real
y imag
Altera Corporation
September 2004