EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 501

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 5–21. Realignment by rx_data_align Node End
Figure 5–22. SYNC Signal Path to Realignment Circuit
Altera Corporation
July 2005
receiver A
receiver B
10× clock
rxloaden
1× clock
SYNC
datain
5
6
0123456789
6
7
TXLOADEN
Receiver Circuit
7
8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
8
× W/J
Realignment
9
9
Circuit
0
0
Register
Parallel
1
1
A state machine can generate the realignment signal to control the
alignment procedure.
realignment signal and the rx_data_align node end.
To guarantee that the rx_data_align signal generated by a user state
machine is latched correctly by the counters, the user circuit must meet
certain requirements.
■
2
2
3
The design must include an input synchronizing register to ensure
that data is synchronized to the
3
4
4
0123456789
SYNC
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
5
× 1
5
6
6
7
Stratix Logic Array
7
8
Register
High-Speed Differential I/O Interfaces in Stratix Devices
8
Array
9
Figure 5–22
9
0
0
10
1
1
2
2
State Machine
3
shows the connection between the
Detection
3
Pattern
×
4
4
1 clock.
Stratix Device Handbook, Volume 2
1234567890
5
SYNC Out
5
6
6
7
7
8
8
Register
9
Hold
9
0
0
1
1
1234567890
2
2
3
3
4
5–29
4