EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 640
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Conclusion
Conclusion
7–62
Stratix Device Handbook, Volume 2
Arithmetic Function Implementation Results
Table 7–19
with the PIPELINE parameter set to YES.
the implementation shown in
set to NO.
Arithmetic Function Design Example
Download the Vector Magnitude Function (magnitude.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
The DSP blocks in Stratix and Stratix GX devices are optimized to support
DSP functions requiring high data throughput, such as FIR filters, IIR
filters and the DCT. The DSP blocks are flexible and configurable in
different operation modes based on the application’s needs. The
TriMatrix memory provides the data storage capability often needed in
DSP applications.
The DSP blocks and TriMatrix memory in Stratix and Stratix GX devices
offer performance and flexibility that translates to higher performance
DSP functions.
Part
Utilization
Performance
Latency
Part
Utilization
Performance
Latency
Table 7–19. Vector Magnitude Function Implementation Results
(PIPELINE=YES)
Table 7–20. Vector Magnitude Function Implementation Results
(PIPELINE=NO)
shows the results of the implementation shown in
EP1S10F780
Lcell: 497/10570 (4%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
194 MHz
15 clock cycles
EP1S10F780
Lcell: 244/10570 (2%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
30 MHz
3 clock cycles
Figure 7–38
Table 7–20
with the PIPELINE parameter
shows the results of
Altera Corporation
September 2004
Figure 7–38
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