EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 572

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Operational Modes
Figure 6–12. Multiply Accumulator Mode
Note to
(1)
6–22
Stratix Device Handbook, Volume 2
Data B
Data A
The signa and signb signals are the same in the multiplier stage and the adder/output block.
shiftoutb
Figure
6–12:
shiftinb
shiftouta
ENA
ENA
D
D
CLRN
CLRN
shiftina
Q
Q
signa (1)
signb (1)
Multiply Accumulator Mode
In multiply accumulator mode, the output of the multiplier stage feeds
the adder/output block, which is configured as an accumulator or
subtractor (see
18-bit multiply accumulators in one DSP block. The Quartus II software
implements smaller multiplier-accumulators by tying the unused low-
order bits of an 18-bit multiplier to ground.
The multiply accumulator output can be up to 52 bits wide for a
maximum 36-bit result with 16-bits of accumulation. In this mode, the
DSP block uses output registers and the accum_sload and overflow
signals. The accum_sload[1..0] signal synchronously loads the
multiplier result to the accumulator output. This signal can be
unregistered or registered once or twice. The DSP block can then begin a
new accumulation without losing any clock cycles. The overflow signal
indicates an overflow or underflow in the accumulator. This signal is
clock
aclr
ena
Figure
ENA
D
CLRN
6–12). You can implement up to two independent
Q
accum_sload1
addnsub1
signa
signb
Accumulator
ENA
ENA
D
D
CLRN
CLRN
Altera Corporation
Q
Q
Data Out
overflow
July 2005