EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 282

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

DLL Specifications
DLL
Specifications
4–102
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
t
ARESET
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2)
Symbol
See
PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output.
Use this equation (f
ranges to determine the allowed PLL settings.
When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
Refer to the section
This parameter is for high-speed differential I/O mode only.
These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
“Maximum Input & Output Clock Rates” on page
Tables 4–131
f
Minimum pulse width on
signal
through 4–133:
O U T
“High-Speed I/O Specification” on page 4–87
= f
Table 4–134
circuit.
For more information on DLL jitter, see the DDR SRAM section in the
Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
Table 4–135
across all PVT conditions. The Stratix DLL can be used below these
frequencies, but it will not achieve the full phase shift requested across all
I N
Parameter
Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit
* ml(n × post-scale counter)) in conjunction with the specified f
Frequency (MHz)
areset
reports the jitter for the DLL in the DQS phase shift reference
lists the Stratix DLL low frequency limit for full phase shift
197 to 200
160 to 196
100 to 159
4–76.
Min
10
for more information.
Max
DLL Jitter (ps)
± 100
± 300
± 500
Altera Corporation
I N P F D
January 2006
and f
V C O
Unit
ns