EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 792

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Quartus II Software Support
12–14
Stratix Device Handbook, Volume 2
Table 12–6. Input Ports of the altremote_update Megafunction (Part 1 of 2)
reset_timer
Port Name
reconfig
clock
reset
Required
Y
Y
Y
N
Logic Array Clock input to the
Logic Array Asynchronous reset, which is used to initialize the remote update
Logic Array When driven logic high, reconfiguration of the device is initiated using
Logic Array This signal is required if you are using the watchdog timer feature. A
Figure 12–10. altremote_update Megafunction Symbol
altremote_update Megafunction
A remote update megafunction, altremote_update, is provided in the
Quartus II software to provide a memory-like interface to allow for easy
control of the remote update parameters.
the input and output ports available on the altremote_update
megafunction.
Source
performed with respects to the rising edge of this clock.
block. To ensure proper operation, the remote update block must be
reset before first accessing the remote update block. This signal is not
affected by the busy signal and will reset the remote update block
even if busy is logic high. This means that if the reset signal is driven
logic high during writing of a parameter, the parameter will not be
properly written to the remote update block.
the current parameter settings in the remote update block. If busy is
asserted, this signal is ignored. This is to ensure all parameters are
completely written before reconfiguration begins.
logic high resets the internal watchdog timer. This signal is not
affected by the busy signal and can reset the timer even when the
remote update block is busy. If this port is left connected, the default
value is 0.
Table 12–8
shows the param[2..0] bit settings.
altremote_update
Description
Tables 12–6
block. All operations are
and
Altera Corporation
September 2004
12–7
describe